In general, a conventional analog-to-digital converter with successive approximation register operation (SAR ADC) is attractive for medium to high bit resolution due to an excellent power efficiency. However, the conventional SAR ADC requires several clock cycle to complete one bit conversion and is also limited to low-bandwidth application. The advance of MOS technology and a 2-b/step design extends the conversion rate to hundreds of MHz. Unfortunately, the need of multiple capacitive digital-to-analog converters (DAC) for the 2-bit SAR ADC results in large input loading. Due to this, the application for higher resolution is constrained. A conventional resistive DAC-based design may be employed to try to alleviate this problem. Unfortunately, a large number of switches and complex routing of the resistive DAC limits its references settling time and conversion rate.